? semiconductor components industries, llc, 2014 august, 2014 ? rev. 0 1 publication order number: esd7461/d esd7461, szesd7461 ultra-low capacitance esd protection micro ? packaged diodes for esd protection the esd7461 is designed to protect voltage sensitive components that require ultra ? low capacitance from esd and transient voltage events. it has industry leading capacitance linearity over voltage making it ideal for rf applications. this capacitance linearity combined with the extremely small package and low insertion loss makes this part well suited for use in antenna line applications for wireless handsets and terminals. features ? industry leading capacitance linearity over voltage ? ultra ? low capacitance: 0.3 pf typ ? insertion loss: 0.05 db at 1 ghz; 0.21 db at 3 ghz ? low leakage: < 1 na ? protection for the following iec standards: ? iec61000 ? 4 ? 2 (esd): level 4 18 kv contact ? iec61000 ? 4 ? 4 (eft): 40 a ? 5/50 ns ? iec61000 ? 4 ? 5 (lightning): 1 a (8/20 s) ? iso 10605 (esd) 330 pf/2 k 23 kv contact ? sz prefix for automotive and other applications requiring unique site and control change requirements; aec ? q101 qualified and ppap capable ? these devices are pb ? free, halogen free/bfr free and are rohs compliant typical applications ? rf signal esd protection ? rf switching, pa, and antenna esd protection ? near field communications ? usb 2.0, usb 3.0 maximum ratings (t a = 25 c unless otherwise noted) rating symbol value unit iec 61000 ? 4 ? 2 (esd) (note 1) 18 kv total power dissipation (note 2) @ t a = 25 c thermal resistance, junction ? to ? ambient p d r ja 300 400 mw c/w junction and storage temperature range t j , t stg ? 55 to +150 c lead solder temperature ? maximum (10 second duration) t l 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. non ? repetitive current pulse at t a = 25 c, per iec61000 ? 4 ? 2 waveform. 2. mounted with recommended minimum pad size, dc board fr ? 4 device package shipping ? ordering information http://onsemi.com ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. esd7461n2t5g xdfn2 (pb ? free) 8000 / tape & reel marking diagram xx = specific device code m = date code xdfn2 case 711am xx m SZESD7461N2T5G xdfn2 (pb ? free) 8000 / tape & reel
esd7461, szesd7461 http://onsemi.com 2 electrical characteristics (t a = 25 c unless otherwise noted) symbol parameter i pp maximum reverse peak pulse current v c clamping voltage @ i pp v rwm working peak reverse voltage i r maximum reverse leakage current @ v rwm v br breakdown voltage @ i t i t test current *see application note and8308/d for detailed explanations of datasheet parameters. bi ? directional tvs i pp i pp v i i r i t i t i r v rwm v c v br v rwm v c v br electrical characteristics (t a = 25 c unless otherwise noted) parameter symbol condition min typ max unit reverse working voltage v rwm 16 v breakdown voltage v br i t = 1 ma (note 3) 16.5 v reverse leakage current i r v rwm = 5 v <1 100 na clamping voltage tlp v c i pp = 8 a (note 4) 35 v clamping voltage tlp v c i pp = 16 a (note 4) 39 v junction capacitance c j v r = 0 v, f = 1 mhz v r = 0 v, f = 1 ghz 0.3 0.3 0.55 0.55 pf dynamic resistance r dyn tlp pulse 1.05 insertion loss f = 1 ghz f = 3 ghz 0.05 0.21 db product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 3. breakdown voltage is tested from pin 1 to 2 and pin 2 to 1. 4. ansi/esd stm5.5.1 ? electrostatic discharge sensitivity testing using transmission line pulse (tlp) model. tlp conditions: z 0 = 50 , t p = 100 ns, t r = 4 ns, averaging window; t 1 = 30 ns to t 2 = 60 ns. figure 1. typical iv characteristics figure 2. typical cv characteristics 1.3 ? 03 1.e ? 04 1.e ? 05 1.e ? 06 1.e ? 07 1.e ? 08 1.e ? 09 1.e ? 10 1.e ? 11 1.e ? 12 ? 30 30 ? 20 20 ? 10 10 0 current (a) voltage (v) 1 18 capacitance (pf) voltage (v) 0.8 0.6 0.4 0.2 0 ? 18 ? 15 ? 12 ? 9 ? 6 ? 30 15 12 9 6 3
esd7461, szesd7461 http://onsemi.com 3 typical characteristics figure 3. typical insertion loss esd7461n2t5g (sod882) figure 4. typical capacitance over frequency esd7461n2t5g (sod882) 1 1.e+07 1.e+10 1.e+08 1.e+09 s21 (db) frequency (hz) 0.5 0 ? 0.5 ? 1 ? 1.5 ? 2 ? 2.5 ? 3 frequency (hz) 1 capacitance (pf) 1.e+07 1.e+10 2.e+09 8.e+09 6.e+09 4.e+09 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
esd7461, szesd7461 http://onsemi.com 4 iec 61000 ? 4 ? 2 spec. level test volt- age (kv) first peak current (a) current at 30 ns (a) current at 60 ns (a) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 i peak 90% 10% iec61000 ? 4 ? 2 waveform 100% i @ 30 ns i @ 60 ns t p = 0.7 ns to 1 ns figure 5. iec61000 ? 4 ? 2 spec figure 6. diagram of esd clamping voltage test setup 50 50 cable tvs oscilloscope esd gun the following is taken from application note and8308/d ? interpretation of datasheet parameters for esd devices. esd voltage clamping for sensitive circuit elements it is important to limit the voltage that an ic will be exposed to during an esd event to as low a voltage as possible. the esd clamping voltage is the voltage drop across the esd protection diode during an esd event per the iec61000 ? 4 ? 2 waveform. since the iec61000 ? 4 ? 2 was written as a pass/fail spec for larger systems such as cell phones or laptop computers it is not clearly de fined in the spec how to specify a clamping voltage at the device level. on semiconductor has developed a way to examine the entire voltage waveform across the esd protection diode over the time domain of an esd pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all esd protection diodes. for more information on how on semiconductor creates these screenshots and how to interpret them please refer to and8307/d.
esd7461, szesd7461 http://onsemi.com 5 figure 7. positive tlp i ? v curve figure 8. negative tlp i ? v curve tlp current (a) v c , voltage (v) 25 040 35 30 51015 25 20 tlp current (a) v c , voltage (v) ? 25 0 ? 45 ? 40 ? 35 ? 5 ? 10 ? 15 ? 30 note: tlp parameter: z 0 = 50 , t p = 100 ns, t r = 300 ps, averaging window: t 1 = 30 ns to t 2 = 60 ns. v iec is the equivalent voltage stress level calculated at the secondary peak of the iec 61000 ? 4 ? 2 waveform at t = 30 ns with 2 a/kv. see tlp description below for more information. 20 15 10 5 0 ? 20 ? 15 ? 10 ? 5 0 45 ? 20 ? 25 transmission line pulse (tlp) measurement transmission line pulse (tlp) provides current versus voltage (i ? v) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. a simplified schematic of a typical tlp system is shown in figure 9. tlp i ? v curves of esd protection devices accurately demonstrate the product?s esd capability because the 10s of amps current levels and under 100 ns time scale match those of an esd event. this is illustrated in figure 10 where an 8 kv iec 61000 ? 4 ? 2 current waveform is compared with tlp current pulses at 8 a and 16 a. a tlp i ? v curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. figure 9. simplified schematic of a typical tlp system dut l s oscilloscope attenuator 10 m v c v m i m 50 coax cable 50 coax cable figure 10. comparison between 8 kv iec 61000 ? 4 ? 2 and 8 a and 16 a tlp waveforms
esd7461, szesd7461 http://onsemi.com 6 package dimensions xdfn2 1.0x0.6, 0.65p (sod ? 882) case 711am issue o a b e d bottom view b l 0.10 c top view 0.05 c a a1 0.10 c 0.10 c c seating plane side view dim min max millimeters a 0.34 0.44 a1 ??? 0.05 b 0.43 0.53 d 1.00 bsc e 0.60 bsc solder footprint* dimensions: millimeters 1.20 0.60 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. 1 l 0.20 0.30 0.47 recommended pin 1 pin 1 indicator e 0.65 bsc a m 0.05 b c a m 0.05 b c 2x e e/2 2x 2x note 3 on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warrant y, representation or guarantee regarding the suitability of it s products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 esd7461/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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